High Speed On-Chip Motion Estimation Co-Processor for H.265/HEVC Standard
| Author | Hammad, Mohamed Nabil | |
|---|---|---|
| metadata.dc.contributor.department | University of Bahrain ,College of Information Technology | |
| metadata.dc.date.accessioned | 2026-09-20T15:49:27Z | |
| Publication date | 2016 | |
| Degree level | Master | |
| Abstract | ABSTRACT H.265/HEVC, or High Efficient Video Coding, has achieved up to 50% savings in the transmitted bit rate compared to the state-of-the-art H.264/AVC video coding standard. As a result, 4K and Ultra High Definition TV (UHD-TV) resolutions can be achieved. Achieving such high bit rate reduction requires the removal of both spatial and temporal redundancies. In this thesis, we focus on the removal of temporal redundancies since they are much more effective than spatial ones. The Motion Estimation (ME) process is used as a temporal redundancies removal tool. Since it consumes up to 84% of the total encoding time, ME is considered the most exhaustive processing unit in the H.265/HEVC encoder There are two main problems when implementing the ME unit hardware in the H.265/HEVC standard: the huge number of data required for performing the ME process and the high computational complexity compared to previous video coding standards. In this thesis, two architectures were implemented to solve these two problems. The first architecture solves the issue of the large number of pixels needed from the external memory in the ME process by using some previous work (Ismail, El-Medany, Al-Junaid, & Abdelgawad, 2014). This is achieved by using a smart data flow that efficiently uses level A and level B data reuse principles. The data reuse principle is mainly used to reduce the I/O memory bandwidth. Consequently, the overall time required to fetch the data from the external memory is greatly reduced. The implemented ME co-processor in the first architecture can perform the ME process at 9 frames per second using 4K (3840×2160) video resolution at 545 MHz. The second architecture which is using previous software verified ASWS algorithm (Goel, Ismail, & Bayoumi, 2005) provides reductions in the computations of the ME process. This is achieved by using a prediction and an Adaptive Search Window Size (ASWS) algorithm. The second architecture can perform the ME process at 10 frame per second using 4K (3840×2160) video resolution at 527 MHz with 100% unity of all hardware components. | |
| metadata.dc.identifier.other | Drupal node 3962 | |
| metadata.dc.identifier.other | https://digitalrepository.uob.edu.bh/en/dar/high-speed-chip-motion-estimation-co-processor-h265hevc-standard | |
| metadata.dc.identifier.uri | http://165.227.56.122/handle/123456789/6904 | |
| Language | en | |
| Link | https://digitalrepository.uob.edu.bh/en/_flysystem/fedora/2025-07/001280_high_speed_on-chip_motion_estimation_co-processor_for_h._265-hevc_standard.pdf | |
| Subject | Coding theory -- Dissertations | |
| Subject | Digital video -- Dissertations | |
| Subject | Thesis (Master) | |
| Subject | Video compression | |
| Title | High Speed On-Chip Motion Estimation Co-Processor for H.265/HEVC Standard | |
| Type | Master's Thesis |
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